This course contains the introductory part of combinational Logic along with the clear concepts of K-Maps and Quine-Mc Cluskey Method. It also introduces sequential networks with flip flops and FSM, FPGA and VHDL, and testing and verification.
8.2. Test vector generation, fault, fault model and fault detection, SA0, SA1, Design for Testability Notes | Digital System Design BSC-CSIT | TU | TABFlux