Course Description

This course contains the introductory part of combinational Logic along with the clear concepts of K-Maps and Quine-Mc Cluskey Method. It also introduces sequential networks with flip flops and FSM, FPGA and VHDL, and testing and verification.

Course Objectives

The course objective is to provide ample knowledge on digital design process and to enhance the knowledge of hardware design in real scenarios.

Course Contents

1. Introduction of logic design

5 hrs

1.1. Introduction of logic design, Digital System and Integration, Electronic Design Automation, IC Manufacturing

1.2. IC Manufacturing, Logic Families, IC Design Techniques

1.3. IC characteristics: fan-out, power dissipation, propagation delay, and noise margin of TTL and CMOS integrated circuit logic devices

2. Review of Boolean Algebra and Combinational Logic

4 hrs

2.1. Review of Boolean Algebra and Combinational Logic, Canonical Form

2.2. Shannon's Expansion, Minterms, Maxterms, Prime Implication

3. Combinational Network Design

5 hrs

3.1. Combinational Network Design: K – Map, Synthesis and Minimization with K – Maps (AND – OR, OR-AND, NAND-NAND, NOR-NOR)

3.2. Standard Combinational Networks

4. Quine-Mc Cluskey Method and Programmable Logic

7 hrs

4.1. Quine- Mc Cluskey Method, Minimization of Boolean expression with Quine-Mc Cluskey method

4.2. PROMs and EPROMs, Programmable Array Logic (PAL), Programmed Logic Array (PLA)

4.3. Gate Arrays, Programmable Gate Array, and Full Custom Design

5. Sequential Networks

8 hrs

5.1. Transition from combinational to sequential network

5.2. Flip-Flops: Direct command, Level Enabled, and Edge-triggered

5.3. Synchronization and Asynchronous Signals

6. Sequential Networks as Finite State Machines

6 hrs

6.1. Standard Models and ASM Diagrams

6.2. Synthesis and Time Behavior of Synchronous FSM

6.3. Design of input forming, Logic and Output Forming Logic of state machine.

7. Field Programmable Gate Arrays (FPGA)

4 hrs

7.1. Field Programmable Gate Arrays (FPGA), VHDL and its use in programmable logic devices (PLDs) like FPGA

8. Testing and Verification

6 hrs

8.1. Testing and Verification, Testing Logic Circuits, Combinational gate testing, Combinational network testing, Sequential Testing

8.2. Test vector generation, fault, fault model and fault detection, SA0, SA1, Design for Testability

Laboratory Works

Implementation of combinational and sequential circuits, FSM, FPGA and VHDL. Testing and verification of circuits.

1.Circuit Implementation
2.VHDL & FPGA

Reference Books

1.Giuliano Donzellini, Luca Oneto, Domenico Ponta, Davide Anguita, Introduction to Digital System Design, Springer
2.Wolf, Wayne, Modern VLSI Design-System on Silicon, Third Edition, Pearson
3.Comer, David J. Digital Logic State Machine Design, Third Edition, Oxford University Press
4.Ashenden, Peter J, The Student's Guide to VHDL, Morgan Kaufman

Digital System Design

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TabFlux . Digital System Design . TU . BSC-CSIT