Computer Architecture

Course Title: Computer Architecture

Course No: CSC213

Nature of the Course: Theory + Lab

Semester: 3

Full Marks: 60 + 20 + 20

Pass Marks: 24 + 8 + 8

Credit Hours: 3

Course Description

This course includes concepts of instruction set architecture, organization or micro-architecture, and system architecture. The instruction set architecture includes programmer’s abstraction of computer. The micro-architecture consist internal representation of computers at register and functional unit level. The system architecture includes organization of computers at the cache and bus level.

Course Objectives

Discuss representation of data and algorithms used to perform operations on data,Demonstrate different operations in terms of Micro-operations, Explain architecture of basic computer and micro-programmed control unit, Understand and memory and I/O organization of a typical computer system, Demonstrate benefits of pipelined systems

Course Contents

1. Data Representation

4 hrs

1.1. Data Representation

Binary Representation

Alphanumeric Representation

Complements

Fixed Point representation

Representing Negative Numbers

Floating Point Representation

Arithmetic with Complements

Overflow

Detecting Overflow

1.2. Other Binary Codes

Gray Code

self Complementing Code

Weighted Code

Excess-3 Code

EBCDIC

1.3. Error Detection Codes

Parity Bit

Odd Parity

Even parity

Parity Generator & Checker

2. Register Transfer and Microoperations

5 hrs

2.1. Register Transfer Concepts

Microoperation

Control Function

2.2. Arithmetic Microoperations

Binary Adder

Binary Adder-subtractor

Binary Incrementer

Arithmetic Circuit

2.3. Logic Microoperations

Logic Microoperations

Hardware Implementation

Applications of Logic Microoperations

2.4. Shift Microoperations

Logical Shift

Circular shift

Arithmetic Shift

Hardware Implementation of Shifter

3. Basic Computer Organization and Design

8 hrs

3.1. Instruction Code

3.2. Operation Code

3.3. Stored Program Concept

3.4. Registers and memory of Basic Computer

3.5. Common Bus System for Basic Computer

3.6. Instruction Format

3.7. Instruction Set Completeness

3.8. Control Unit of Basic Computer

3.9. Control Timing Signals

3.10. Instruction Cycle of Basic computer

3.11. Determining Type of Instruction

3.12. Memory Reference Instructions

3.13. Input-Output Instructions

3.14. Program Interrupt & Interrupt Cycle

3.15. Description and Flowchart of Basic Computer

4. Microprogrammed Control

4 hrs

4.1. Control Word

4.2. Microprogram

4.3. Control Memory

4.4. Control Address Register

4.5. Sequencer

4.6. Address Sequencing

4.7. Conditional Branch

4.8. Mapping of Instructions

4.9. Subroutines

4.10. Microinstruction Format

4.11. Symbolic Microinstructions

4.12. Design of Control Unit

5. Central Processing Unit

4 hrs

5.1. Major Components of CPU

5.2. CPU Organization

5.3. Instruction Formats

5.4. Addressing Modes

5.5. Data Transfer and manipulation

5.6. Program Control

5.7. Subroutine Call and Return

5.8. Types of Interrupt

5.9. RISC vs CISC

5.10. Pros and Cons of RISC and CISC

5.11. Overlapped Register Windows

6. Pipelining

6 hrs

6.1. Parallel Processing

6.2. Multiple Functional Units

6.3. Flynn’s Classification

6.4. Pipelining: Concept and Demonstration with Example

6.5. Speedup Equation

6.6. Floating Point addition and Subtraction with Pipelining

6.7. Instruction Level Pipelining

6.8. Three & Four-Segment Instruction Pipeline

6.9. Pipeline Conflicts and Solutions

6.10. Vector Processing

6.11. Applications

6.12. Vector Operations

6.13. Matrix Multiplication

7. Computer Arithmetic

6 hrs

7.1. Addition and Subtraction with Signed Magnitude Data

7.2. Addition and Subtraction with Signed 2’s Complement Data

7.3. Multiplication of Signed Magnitude Data

7.4. Booth Multiplication

7.5. Division of Signed magnitude Data

7.6. Divide Overflow

8. Input Output Organization

4 hrs

8.1. I/O Bus and Interface

I/O Bus and Interface Modules

I/O vs. Memory Bus

Isolated vs. Memory-Mapped I/O

8.2. Asynchronous Data Transfer

Asynchronous Data Transfer: Strobe

Handshaking

8.3. Modes of Transfer

Programmed I/O

Interrupt-Initiated I/O

Direct memory Access

8.4. Priority Interrupt

Polling

Daisy-Chaining

Parallel Priority Interrupt

8.5. Direct Memory Access and IOP

Direct Memory Access

Input-Output Processor

DMA vs. IOP

9. Memory Organization

4 hrs

9.1. Memory Hierarchy and Main Memory

Memory Hierarchy

Main Memory

RAM and ROM Chips

Memory address Map

Memory Connection to CPU

9.2. Auxiliary and Associative Memory

Auxiliary Memory (magnetic Disk, Magnetic Tape)

Associative Memory: Hardware Organization

Match Logic

Read Operation

Write Operation

9.3. Cache Memory

Cache Memory: Locality of Reference

Hit & Miss Ratio

Mapping

Write Policies

Laboratory Works

The laboratory work includes implementing and simulating the algorithms, studied in the course, by using high level languages like C or VHDL. The laboratory works should include at least following concepts

1.Simulate features like overflow, data representation by using VHDL
2.Simulate design of different units by using VHDL
3.Simulate pipelining by using VHDL
4.Implement algorithms for computer arithmetic using high level language like C or C++

Text Books

1.M. Morris Mano, Computer System Architecture, Prentice-Hall of India, Pvt. Ltd., Third edition, 2007

Reference Books

1.William Stallings, Computer Organization and Architecture, Prentice-Hall of India, Pvt. Ltd., Seventh edition, 2005
2.Vincent P. Heuring and Harry F. Jordan, Computer System Design and Architecture, Prentice-Hall of India, Pvt. Ltd., Second edition, 2003

Notes:

This syllabus follows the official B.Sc. CSIT curriculum of Tribhuvan University. In case of any doubt or revision, the university’s published syllabus shall be considered authoritative.

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Computer Architecture

Course Description

Course Objectives

Course Contents

Laboratory Works

Text Books

Reference Books

Notes: